The present invention relates generally to a method and apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations.
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology, designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
As shown in FIG. 1, SOI semiconductors include a thin layer of silicon placed on top of an insulator, such as silicon dioxide (SiO2) or glass, and a MOS transistor built on top of this structure. The main advantage of constructing the MOS transistor on top of an insulator layer is to reduce the internal capacitance of the transistor. This is accomplished by placing the insulator oxide layer between the silicon substrate and the impurities required for the device to operate as a transistor. Reducing the internal capacitance of the transistor increases its operating speed. With SOI technology, faster MOS transistors can be manufactured resulting in faster electronic devices.
A problem called bipolar discharge exists with SOI FETs. An inherent drawback of placing a MOS transistor on top of a SOI layer is that the MOS transistor is actually placed in parallel with a parasitic bipolar junction transistor, as illustrated in FIG. 2. The parasitic bipolar transistor can cause the unwanted parasitic bipolar current, which alters the speed and lowers noise margin in a dynamic CMOS circuit.
Normally, parasitic bipolar action does not manifest itself in conventional bulk CMOS transistors because the base of the bipolar transistor is always kept at ground potential, keeping the bipolar transistor turned off. In the SOI FET, the body (B) of the MOS FET device, or base of the bipolar transistor, is floating and can be charged high by junction leakages induced when both drain (D) and source (S) terminals of the MOS FET are at a high potential. Subsequently, if the source (S) is pulled to a low potential, the trapped charge in the body (B) is available as base current for the parasitic bipolar transistor. The parasitic base current activates the bipolar transistor and generates a collector current at the drain terminal of the MOS FET. This collector current flow in the bipolar junction transistor or bipolar discharge is undesirable since it causes an unintended loss of charge on the drain node of a dynamic circuit. Such parasitic bipolar current reduces the noise margin of the dynamic circuit and can result in the functional failure.
SOI passgate transistors suffer initial cycle parasitic bipolar current, which causes serious noise, timing and performance concerns. The adverse effects are most severe when the circuit is initially turned on after being idle for a long period of time, for example, for a time scale in the range of milliseconds. This is because the floating body of the SOI field effect transistor can develop a body charge over time. The amount of such body charge will depend on the potentials at the source, drain, and gate terminal electrodes of the SOI field effect transistor. The maximum amount of charging occurs when the gate is completely turned off and both the source and drain electrodes are biased at the highest voltage supply Vdd.
A need exists for an improved method and apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations.
A principal object of the present invention is to provide a method and apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations. Other important objects of the present invention are to provide such method and apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for implementing enhanced silicon-on-insulator (SOI) passgate operations. The apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations includes a silicon-on-insulator (SOI) passgate field effect transistor. A select input is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. A discharging field effect transistor of the opposite channel type is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is activated during an off cycle of the silicon-on-insulator (SOI) passgate field effect transistor.
In accordance with features of the invention, the discharging field effect transistor is coupled to the body of the SOI passgate field effect transistor. The discharging field effect transistor is deactivated during an on cycle of the SOI passgate field effect transistor, whereby the body of the SOI passgate field effect transistor floats during the on cycle with a higher-than-ground starting body potential, which enables the low threshold operation from the beginning of the on cycle.